Signal Integrity

Signal Integrity

Signal Integrity

The interconnects operating at high frequency and fast switching rates demand SI analysis for right design at first time. Caliber Interconnect's SI engineers are having strong knowledge in SI theory and expertise in simulation tools to analyze various SI/PI issues like reflection due to impedance mismatch, crosstalk, signal attenuation and PDN noise which affects the interconnect performance. The analysis is carried out in two phase, the pre and post layout analysis.

Pre-layout analysis

Planning the stack-up for controlled impedance, dielectric material selection for high frequency operation, I/O buffer selection from different drive strength, topology optimization, termination strategy, routing specifications (Trace width, spacing and length matching) and floor planning for critical components are various sections in pre-layout analysis.

Post layout analysis

Post layout analysis includes simulations of routed board for potential SI/PI issues like reflection, overshoot/undershoot, crosstalk, attenuation, EMI and PDN issues. The post layout report is prepared from simulation results along with suggestions for topology modification, termination schemes and layout modification to achieve good signal and power integrity for any SI/PI issues.

High speed channel modeling

high speed channel modelling

Caliber SI engineers are very much familiar with high speed channel modelling considering backplane, Add-in Card, via breakout, connectors and cables. Using highly accurate Ansys and Sigrity 3D simulation tools, we can do correct and optimized channel so as to keep the channel loss within the spec. Also long SERDES channel with high data rate need use of different TX pre-emphasis, RX CTLE gain and DFE equalization tap factors so that the eye opening is good at the Receiver end. This features are available in the ibis ami models. We have good experience in ami parameter variation and optimization for SERDES channel to keep the channel within the eye spec with the help of market leading simulation tools of latest versions.

PCB/Package

Signal Integrity Analysis

  • Reflection, Ringing and Overshoot/Undershoot
  • Single ended and Differential Crosstalk Analysis
  • Signal Attenuation due to IR-Drop, Skin-effect and Dielectric Loss
  • Channel Analysis for Serial Communication – Eye Diagram Analysis
  • IBIS/IBIS-AMI based system SI
  • Clock Analysis
    • Common Clocking
    • Source Synchronous Clocking
  • DDR Timing Analysis
  • S-parameter Analysis
    • Return loss, Insertion loss, NEXT and FEXT analysis
    • Mixed mode Analysis for differential channel: Differential mode , common mode
  • Coupling analysis – Single and differential analysis
  • Co-design (IC/package/board)

Power Integrity Analysis (PI Analysis)

  • SSN Analysis
  • IR- Drop Analysis
  • Power Distribution Network Impedance profile Analysis
  • Transient noise estimation
  • Parasitic RLGC extraction
  • De-coupling Capacitors Estimation and Placement Optimization

EMI/EMC Analysis

  • Net-wise radiated EMI Analysis
  • EMC Analysis based on FCC, CISPR and VCCI Requirements

Interfacing Technologies

We have experience in carrying simulations involving the following interfaces:

  • SDRAM, QDR, DDR2, DDR3 & DDR4 technology, eMMC
  • PCI, PCI-X, PCIe
  • MIPI, CSI, HDMI
  • FSB, Hub, Interface
  • USB, USB-OTG, HT, SATA, SAS
  • SERDES, XAUI, RocketIO, Aurora, Gigabit Ethernet
  • SRIO, CPRIO
  • Simulations involving QSFP/ SFP optical modules
  • Simulations using Firefly connectors
  • 28Gbps channel simulation using IBIS/ AMI models
  • Simulation of higher frequency (up to 100GHz) RF channels

Analysis Tools Expertise

  • Cadence Allegro PCB SI/PI
  • Cadence Allegro Package SI/PI along with Paksi 3D
  • Cadence Allegro SiP SI/PI along with Paksi 3D
  • Cadence Allegro SigXplorer
  • Mentor Graphics Hyperlynx
  • LTSpice
  • Ansys Electromagnetic 15.0
  • Cadence Sigrity Tool