Design Verification(Silicon FrontEnd–DV)
Our ASIC/FPGA verification experts will assist you in creating test plan and test benches to assist your team to overcome the design errors with suggestions. Our flexible business model allows you to chose onsite or offsite consultants.
- Design verification (DV) at RTL level
- Design Verification at gate level (i.e. Gate Level Simulations – both unit delay and SDF annotated).
- Power Aware Verification.
- Formal Verification
- Experience in Verification infrastructure development (including stimulus generator, driver, monitor, scoreboard, assertions, CP coding)
- Experience in Languages like Verilog, System Verilog, Specman, Vera, C++, C and system C.
- Experience with tools like Modelsim, NCSim, VCS, Debussy, MVSIM, MVRC, JasperGold.
- Senior Management have Experience of more than 12 years in DV area
Design for Test and Debug(DFT/DFD)
High complex ASIC/SOC devices which contains millions of logic and functional blocks operating at high frequency needs a proper test strategy to achieve optimized fault coverage. Our DFT consultants provide solutions for the increasing complexity of test challenges in IC designs.
- DFT & DFD ARCHITECTURE/PLANNING
- Top leadership has experience of more than 22 years which includes working in several well known North American product companies(like AMD/GENESIS/TERANETICS/PLX) in DFT/DFD Principal architect position.
- Handled more than 50 design from architecture to silicon bring-up including high speed processors/mixed signal SOC products.
- TAP Controller(BSCAN )insertion.
- ANALOG DFT.
- DFD /LIKE TEST BUS PLAN /SCAN DUMP etc.
- RO /LBIST definition and spec
- DFT mode STA
- Multiple clock domain/power domain handling
- Pattern debug/yield enhancement
- RMA analysis
- —DFT/DFD Architecture
- —SCAN insertion & ATPG pattern generation
- —MBIST with Repair